MEMSYS 2016

Conference Schedule

Mon Oct 3

5:00 – 9:00 pm   Welcome Reception in the Courtyard

Tue Oct 4

7:15 am Breakfast in the Bombay Room and in the Courtyard

8:15 am Opening Remarks

8:20 am Software Keynote: Richard Vuduc

Computational Science and Engineering
Georgia Institute of Technology

9:20 am  Break

Session 1: Issues in High Performance Computing
Session Chair: David Donofrio, Berkeley Lab

9:40 am Large-Memory Nodes for Energy Efficient High-Performance Computing
Darko Zivanovic (Barcelona Supercomputing Center (BSC) Universitat Politecnica de Catalunya (UPC)), Milan Radulovic (BSC and UPC), German Llort (BSC and UPC),
David Zaragoza (BSC and UPC), Janko Strassburg (BSC), Paul Carpenter (BSC), Petar Radojkovic (BSC), Eduard Ayguade (BSC and UPC)

10:00 am A New Metric to Measure Cache Utilization for HPC Workloads
Aditya Deshpande (University of Southern California), Jeffrey Draper (University of Southern California)

10:20 am Checkpointing Exascale Memory Systems with Existing Memory Technologies 
Nilmini Abeyratne (University of Michigan), Hsing-Min Chen (Arizona State University), Byoungchan Oh (University of Michigan), Ronald Dreslinski (University of Michigan), Chaitali Chakrabarti (Arizona State University), Trevor Mudge (University of Michigan)

10:40 am Exposing the Locality of Heterogeneous Memory Architectures to HPC Applications
Brice Goglin (INRIA, Institut National de Recherche en Informatique et en Automatique)

11:00 am Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC
Kazi Asifuzzaman (Barcelona Supercomputing Center (BSC) and Universitat Politecnica de Catalunya (UPC)), Milan Pavlovic (BSC and UPC), Milan Radulovic (BSC and UPC), David Zaragoza (BSC and UPC), Ohseong Kwon (Samsung Electronics Co. Ltd), Kyung-Chang Ryoo (Samsung Electronics Co. Ltd), Petar Radojkovic (BSC)

11:20 am Nswap2L: Transparently Managing Heterogeneous Cluster Storage Resources for Fast Swapping
Tia Newhall (Swarthmore College), Edward Lehman-Borer (Swarthmore College), Benjamin Marks (Swarthmore College)

11:40 am Low Latency, High Bisection Bandwidth Networks for Exascale Memory Systems 
Shang Li (University of Maryland), Po-Chun Huang (University of Maryland), David Banks (University of Maryland), Max DePalma (University of Maryland), Ahmed Elshaarany (University of Maryland), Scott Hemmert (Sandia National Labs), Arun Rodrigues (Sandia National Labs), Emily Ruppel (University of Maryland), Yitian Wang (University of Maryland), Jim Ang (Sandia National Labs), Bruce Jacob (University of Maryland)

12:00pm Conference Lunch in the Courtyard

Session 2: Nonvolatile Main Memories and DRAM Caches, Part I
Session Chair: Wendy Elsasser, ARM

1:00 pm Write Locality and Optimization for Persistent Memory 
Dong Chen (University of Rochester), Chencheng Ye (University of Rochester), Chen Ding (University of Rochester)

1:20 pm Multi-Level Memory Policies: What You Add Is More Important Than What You Take Out
Simon Hammond (Sandia National Labs), Arun Rodrigues (Sandia National Labs), Gwendolyn Voskuilen (Sandia National Labs)

1:40 pm DRAMPersist: Making DRAM Systems Persistent
Krishna T. Malladi (Samsung Semiconductor, Inc), Manu Awasthi (Samsung Semiconductor, Inc), Hongzhong Zheng (Samsung Semiconductor, Inc)

2:00 pm Fast Full System Memory Checkpointing with SSD-aware Memory Controller
Jim Stevens (University of Maryland), Paul Tschirhart (University of Maryland), Bruce Jacob (University of Maryland)

2:20 pm Challenges of Programming a System with Heterogeneous Memories and Heterogeneous Processors
Shuai Che (AMD), Arkaprava Basu (AMD), Jonathan Gallmeier (AMD)

2:40 pm Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems
Amin Farmahini-Farahani (AMD Research), David Roberts (AMD Research), Nuwan Jayasena (AMD Research)

3:00 pm Break

Session 3: Hybrid Memory Cube and Alternative DRAM Channels
Session Chair: Scott Lloyd, Lawrence Livermore

3:20 pm Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories
Dmitry Knyaginin (Chalmers University of Technology), Vassilis Papaefstathiou (Chalmers University of Technology), Per Stenstrom (Chalmers University of Technology)

3:40 pm Co-DIMM: Inter-socket Data Sharing via a Common DIMM Channel 
Ke Zhang (Institute of Computing Technology, Chinese Academy of Sciences), Lei Yu (Institute of Computing Technology, Chinese Academy of Sciences), Yisong Chang (Institute of Computing Technology, Chinese Academy of Sciences), Ran Zhao (Institute of Computing Technology, Chinese Academy of Sciences), Hongxia Zhang (Institute of Computing Technology, Chinese Academy of Sciences), Lixin Zhang (Institute of Computing Technology, Chinese Academy of Sciences), Mingyu Chen (Institute of Computing Technology, Chinese Academy of Sciences), Sally A. McKee (Chalmers University of Technology)

4:00 pm Exploring Time and Energy for Complex Accesses to a Hybrid Memory Cube 
Juri Schmidt (University of Heidelberg), Holger Froening (University of Heidelberg), Ulrich Bruening (University of Heidelberg)

4:20 pm Analyzing Consistency Issues In HMC Atomics 
Pranith Kumar (Georgia Institute of Technology), Lifeng Nai (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology)

4:40 pm Exploring Tag-Bit Memory Operations in Hybrid Memory Cubes 
John Leidel (Texas Tech University), Yong Chen (Texas Tech University)

5:00 pm Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems
Zehan Cui (Institute of Computing Technology, Chinese Academy of Sciences), Tianyue Lu (Institute of Computing Technology, Chinese Academy of Sciences), Sally A. McKee (Chalmers University of Technology), Mingyu Chen (Institute of Computing Technology, Chinese Academy of Sciences), Haiyang Pan (Institute of Computing Technology, Chinese Academy of Sciences), Yuan Ruan (Institute of Computing Technology, Chinese Academy of Sciences)

5:20 pm Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture 
Xi Wang (Texas Tech University), John D. Leidel (Texas Tech University), Yong Chen (Texas Tech University)

Break 5:40 pm

6:00 – 7:30 pm Spirited Discussion
Memory Systems Problems and Solutions

• Chen Ding, U. Rochester
• Wendy Elsasser, ARM
• Hillery Hunter, IBM
• Mike O’Connor, NVIDIA
• Dave Resnick, Micron & Sandia

8:00 pm Dinner — Regular attendees on your ownProgram Committee dinner meeting — Chart House, Alexandria

Wed Oct 5

7:15 am Breakfast in the Bombay Room and in the Courtyard 

8:20am Hardware Keynote: J. Thomas Pawlowski Chief Technologist/Micron Fellow Architecture Development, Micron

9:20am Break

Session 4: Nonvolatile Main Memories and DRAM Caches, Part II
Session Chair: Maya Gokhale, Lawrence Livermore

9:40 am Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache
Seunghee Shin (North Carolina State University), Sihong Kim (Samsung Electronics Corporation), Yan Solihin (North Carolina State University)

10:00 am Analyzing Allocation Behavior for Multi-level Memory
Gwendolyn Voskuilen (Sandia National Laboratories), Arun Rodrigues (Sandia National Laboratories), Simon Hammond (Sandia National Laboratories)

10:20 am Processing Acceleration with Resistive Memory-based Computation
Mohsen Imani (University of California San Diego), Yan Cheng (University of California San Diego), Tajana Rosing (University of California San Diego)

10:40 am The Case for Associative DRAM Caches
Paul Tschirhart (University of Maryland), Jim Stevens (University of Maryland), Zeshan Chishti (Intel Labs), Bruce Jacob (University of Maryland)

11:00 am Prefetching as a Potentially Effective Technique for Hybrid Memory Optimization 
Mahzabeen Islam (University of North Texas), Soumik Banerjee (Advanced Micro Devices), Mitesh Meswani (Advanced Micro Devices), Krishna Kavi (University of North Texas)

11:20 am Replacement Policies for Heterogeneous Memories
Jacob Brock (University of Rochester), Chencheng Ye (University of Rochester), Chen Ding (University of Rochester)

11:40 am How Many MLCs Should Impersonate SLCs to Optimize SSD Performance? 
Wei Wang (San Diego State University), Tao Xie (San Diego State University), Wen Pan (San Diego State University), Deng Zhou (San Diego State University)

12:00 pm Conference Lunch in the Courtyard

1:00 pm  Session 5: Thinking Outside the Box
Session Chair: Sally McKee, Chalmers

1:00 pm Languages Must Expose Memory Heterogeneity
Xiaochen Guo (Lehigh University), Aviral Shrivastava (Arizona State University), Michael Spear (Lehigh University), Gang Tan (Pennsylvania State University)

1:20 pm ConGen: An Application Specific DRAM Memory Controller Generator 
Matthias Jung (University of Kaiserslautern), Deepak M. Mathew (University of Kaiserslautern), Christian Weis (University of Kaiserslautern), Norbert Wehn (University of Kaiserslautern), Irene Heinrich (University of Kaiserslautern), Marco V. Natale (University of Kaiserslautern), Sven O. Krumke (University of Kaiserslautern)

1:40 pm Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud
Yin Li (Rensselaer Polytechnic Institute), Hao Wang (Rensselaer Polytechnic Institute), Xiaoqing Zhao
(Xi’an Jiaotong University), Hongbin Sun (Xi’an Jiaotong University), Tong Zhang (Rensselaer
Polytechnic Institute)

2:00 pm Software Assisted Hardware Cache Coherence for Heterogeneous Processors 
Arkaprava Basu (AMD Research), Sooraj Puthoor (AMD Research), Shuai Che (AMD Research), Bradford Beckmann (AMD Research)

2:20 pm Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging
Rishiraj Bheda (Georgia Institute of Technology), Tom Conte (Georgia Institute of Technology), Jeffrey Vetter (Oak Ridge National Laboratory)

2:40 pm Data-Centric Computing Frontiers: A Survey On Processing-In-Memory
Patrick Siegl (TU Braunschweig), Rainer Buchty (TU Braunschweig), Mladen Berekovic (TU Braunschweig)

3:00 pm Break

3:20 pm Session 6: Improving the DRAM Device Architecture 
Session Chair: Arun Rodrigues, Sandia

3:20 pm HAPPY: Hybrid Address-based Page Policy in DRAMs
Mohsen Ghasempour (The University of Manchester), Aamer Jaleel (Nvidia), Jim D. Garside (The University of Manchester), Mikel Lujan (The University of Manchester)

3:40 pm AWARD: Approximation-aWAre Restore in Further Scaling DRAM
Xianwei Zhang (University of Pittsburgh), Youtao Zhang (University of Pittsburgh), Bruce Childers (University of Pittsburgh), Jun Yang (University of Pittsburgh)

4:00 pm DRAMScale: Mechanisms to Increase DRAM Capacity
Krishna T. Malladi (Samsung Semiconductor, Inc), Uksong Kang (Samsung Semiconductor, Inc), Manu Awasthi (Samsung Semiconductor, Inc), Hongzhong Zheng (Samsung Semiconductor, Inc)

4:20 pm On the Use of DRAM with Unrepaired Weak Cells in Computing Systems 
Hao Wang (Renssealer Polytechnic Insitutute), Yin Li (Renssealer Polytechnic Insitutute), Xuebin Zhang (Renssealer Polytechnic Insitutute), Xiaoqing Zhao (Xi’an Jiaotong University), Hongbin Sun (Xi’an Jiaotong University), Tong Zhang (Renssealer Polytechnic Insitutute)

4:40 pm CLARA: Circular Linked-List Auto and Self Refresh Architecture
Aditya Agrawal (Nvidia Corporation), Mike O’ Connor (Nvidia Corporation), Evgeny Bolotin (Nvidia Corporation), Niladrish Chatterjee (Nvidia Corporation), Joel Emer (Nvidia Corporation), Steve Keckler (Nvidia Corporation)

5:00 pm MicroRefresh: Minimizing Refresh Overhead in DRAM Caches
Nagendra Gulur (Texas Instruments), R. Govindarajan (Indian Institute of Science), Mahesh Mehendale (Texas Instruments)

5:20 pm DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs
Mohsen Ghasempour (The University of Manchester), Jim D. Garside (The University of Manchester), Aamer Jaleel (Nvidia), Mikel Lujan (The University of Manchester)

5:40 pm Break 

6:00 – 7:30 pm Spirited Discussion
New and Cool Memory Technologies
• David Chapman, Tezzaron Semiconductor
• Paolo Faraboschi, Hewlett Packard Enterprise
• Frank Hady, Intel
• David Stauffer, Kandou Bus
• Robert Voigt, Northrop Grumman

7:45 pm Conference Dinner & Awards

Thu Oct 6

7:15 am Breakfast in the Bombay Room and in the Courtyard

8:20 am Session 7: Issues and Interconnects for 2.5D and 3D Packaging
Session Chair: Robert Voigt, Northrop Grumman

8:20 am Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip 
Paolo Grani (University of California, Davis), Roberto Proietti (University of California, Davis), Venkatesh Akella (University of California, Davis), S. J. Ben Yoo (University of California, Davis)

8:40 am Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems
Syed Minhaj Hassan (Geogria Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology)

9:00 am Reliability and Performance Trade-off Study of Heterogeneous Memories
Manish Gupta (University of California San Diego), David Roberts (Advanced Micro Devices), Mitesh Meswani (Advanced Micro Devices), Vilas Sridharan (Advanced Micro Devices), Dean Tullsen (University of California San Diego), Rajesh Gupta (University of California San Diego)

9:20 am Integrated Thermal Analysis for Processing In Die-Stacking Memory
Yuxiong Zhu (University of California, Santa Cruz), Borui Wang (University of California, Santa Cruz), Dong Li (University of California, Merced), Jishen Zhao (University of California, Santa Cruz)

9:40 am TAPAS: Temperature-aware Adaptive Placement for 3D Stacked Hybrid Caches
Majed Valad Beigi (Northwestern University), Gokhan Memik (Northwestern University)

10:00 am Break

10:20 am Session 8: Some Amazingly Cool Physical Experiments
Session Chair: David Donofrio, Berkeley Lab

10:20 am Characterizing the Performance of Hybrid Memory Cube Using ApexMAP Application Probes
Khaled Ibrahim (Lawrence Berkeley National Lab), Farzad Fatollahi-Fard (Lawrence Berkeley National Laboratory), David Donofrio (Lawrence Berkeley National Laboratory), John Shalf (Lawrence Berkeley National Laboratory)

10:40 am Evaluating the Feasibility of Storage Class Memory as Main Memory
Scott Lloyd (Lawrence Livermore National Laboratory), Maya Gokhale (Lawrence Livermore National Laboratory)

11:00 am Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits
Dietmar Fey (Friedrich-Alexander University Erlangen-Nuremberg), Marc Reichenbach (Friedrich-Alexander University Erlangen-Nuremberg), Christopher Söll (Friedrich-Alexander University Erlangen-Nuremberg), Mehrdad Biglari (Friedrich-Alexander University Erlangen-Nuremberg), Jürgen Röber (Friedrich-Alexander University Erlangen-Nuremberg), Robert Weigel (Friedrich-Alexander
University Erlangen-Nuremberg)

11:20 am A Validation of DRAM RAPL Power Measurements
Spencer Desrochers (University of Maine), Chad Paradis (Garmin Ltd.), Vincent Weaver (University of Maine)

11:40 am Reverse Engineering of DRAMs: Row Hammer with Crosshair
Matthias Jung (University of Kaiserslautern), Carl C. Rheinländer (University of Kaiserslautern), Christian Weis (University of Kaiserslautern), Norbert Wehn (University of Kaiserslautern)

12:00 pm Closing Remarks