Keynote Speakers and Panelists 2018


Keynote Speakers


Brian Barrett

Brian Barrett is a Principal Engineer at Amazon Web Services, focused on High Performance Computing. Brian joined AWS in 2014, with a focus on improving network performance in EC2 and, more recently, improving the HPC application lifecycle in AWS. Prior to joining Amazon, Brian was a Principal Member of Technical Staff in the Scalable System Software group at Sandia National Laboratories, co-developing the Portals 4.0 Network Programming Interface and researching techniques for improving application scalability through better network designs. Brian is one of the original authors of the Open MPI implementation of the MPI standard.

Steven J. Wallach

Steven J. Wallach was a founder of Convey Computer. Micron Technologies bought Convey in 2015. At Micron, Wallach is a design-engineering director. Previously, he served as vice president of technology for Chiaro Networks Ltd., and as co-founder, chief technology officer and senior vice president of development of Convex Computer Corporation. After Hewlett-Packard Co. bought Convex, Wallach became chief technology officer of HP’s Enterprise Systems Group. Wallach served as a consultant to the U.S. Department of Energy’s Advanced Simulation and Computing Program at Los Alamos National Laboratory from 1998 to 2007. He was also a visiting professor at Rice University in 1998 and 1999, and was manager of advanced development for Data General Corporation. His efforts on the MV/8000 are chronicled in Tracy Kidder's Pulitzer Prize winning book, "The Soul of a New Machine." Wallach, who has 40 patents, is a member of the National Academy of Engineering, an IEEE Fellow, and was a founding member of the Presidential Information Technology Advisory Committee. He is the 2008 recipient of IEEE’s Seymour Cray Award and the 2002 Charles Babbage award.

Thomas Pawlowski

Thomas Pawlowski is a Fellow and Chief Technologist with Micron’s Architecture Development Group. His responsibilities include evaluating new technologies and investments, exploring new memory and system architectures, and providing guidance to many technical teams, both internally and external to Micron.

Mr. Pawlowski’s experience includes the creation or co-creation of numerous groundbreaking memory architectures and concepts including: synchronous burst pipelined SRAM; hierarchical cache systems; Zero Bus Turnaround SRAM; abstracted memory; the first double data rate memory (starting with SRAM and extending to DRAM and NAND technologies); Pseudo-Static RAM; high-speed NAND; the first double address rate memory; the first quad data rate memory; the first multi-channel memory; memories on SERDES buses; RLDRAM (the first DRAM to exceed SRAM performance); refresh and error correction schemes for memory subsystems; the first 3D memory concept; root hardware architecture of Micron’s newly announced nondeterministic Finite Automata Processor; and other projects still in development.

Mr. Pawlowski earned a bachelor of applied science degree in electrical engineering, summa cum laude, from the University of Waterloo in Canada. He has well over 100 U.S. and in-flight patents and serves on several advisory boards and conference program committees such as MICRO, ISCA and others.

In his spare time, Mr. Pawlowski designs and builds loudspeakers, custom tools, and he has completed 75% of the design and fabrication of a revolutionary electric car concept.


Panelists


Keren Bergman

Keren Bergman is the Charles Batchelor Professor of Electrical Engineering at Columbia University where she also serves as the Faculty Director of the Columbia Nano Initiative. Prof. Bergman received her Ph.D. from M.I.T. She joined Columbia in 2002, where she leads the Lightwave Research Laboratory encompassing multiple cross-disciplinary programs at the intersection of computing and photonics. Bergman serves on the Leadership Council of the American Institute of Manufacturing (AIM) Photonics leading projects that support the institute’s silicon photonics manufacturing capabilities and Datacom applications. She is a Fellow of the Optical Society of America (OSA) and IEEE.

Phil Emma

Dr. Philip Emma is a Fellow of the Institute of Electrical and Electronics Engineers. He recently retired as Chief Scientist from IBM TJ Watson Research Center in Yorktown Heights, NY. While his primary focus has been architecture and microarchitecture, he’s done work in many other areas throughout his career, including circuit design, packaging, memory, and transmission lines. He holds over 200 patents and has written parts of four books on these topics. He’s currently working on a book on quantum mechanics, as well as on his second novel.

Adolfy Hoisie

Adolfy Hoisie is a Department Chair at the Brookhaven National Laboratory, where he directs the Computing for National Security Department. Before joining Brookhaven, he was with the Pacific Northwest National Laboratory where he directed the Advanced Computing, Mathematics, and Data Division and was a Laboratory Fellow. Prior to PNNL, he served in a variety of scientific and leadership positions at Los Alamos National Laboratory, including director of the Center for Advanced Architectures and Usable Supercomputing and leader of the Computer Science for High-Performance Computing Group and its Performance and Architecture Laboratory.

Adolfy is an internationally recognized expert in performance analysis, modeling, and engineering of extreme-scale parallel computing systems and applications and system architecture. He has served as the principal investigator of projects with diverse funding sources, including the U.S. Department of Energy’s Office of Advanced Scientific Computing Research, National Nuclear Security Administration,
Defense Advanced Research Projects Agency, National Science Foundation, and U.S. Department of Defense, among others. He has pioneered methods in his areas of expertise, creating practical, highly accurate performance modeling techniques that have set the standard in the community. Adolfy is a past winner of the Gordon Bell Award and has served extensively in the high-performance computing community in various capacities, including conference organizer, editorial board member, committee and panel member, and on advisory boards. He has published extensively in peer-reviewed literature and co-authored three books. In 2017, he was named one of a dozen “People to Watch” by HPCwire, a source for global news and information about high-performance computing.

Jeffrey Vetter

Jeffrey Vetter, Ph.D., is a Distinguished R&D Staff Member at Oak Ridge National Laboratory (ORNL). At ORNL, Vetter is the founding group leader of the Future Technologies Group in the Computer Science and Mathematics Division. Vetter also holds joint appointments at the Georgia Institute of Technology and the University of Tennessee-Knoxville. Vetter earned his Ph.D. in Computer Science from the Georgia Institute of Technology. Vetter is a Fellow of the IEEE, and a Distinguished Scientist Member of the ACM. In 2010, Vetter, as part of an interdisciplinary team from Georgia Tech, NYU, and ORNL, was awarded the ACM Gordon Bell Prize. Also, his work has won awards at major conferences including Best Paper Awards at the International Parallel and Distributed Processing Symposium (IPDPS), the AsHES workshop, and EuroPar, Best Student Paper Finalist at SC14, and Best Presentation at EASC 2015. In 2015, Vetter served as the SC15 Technical Program Chair. His recent books, entitled "Contemporary High Performance Computing: From Petascale toward Exascale (Vols. 1 and 2)," survey the international landscape of HPC. See his website for more information: http://ft.ornl.gov/~vetter/.

Shekhar Borkar

Shekhar Borkar is a senior director of technology at Qualcomm Inc. working on special projects for energy efficient data analytics. Shekhar is a fellow of IEEE.

Wendy Elsasser

Wendy Elsasser has over 20 years of experience in design and architecture with a focus on memory sub-systems for the last 15 years. She has been working at Arm for the last 4 ½ years in the Memory and Systems Research group. Her work includes analysis of emerging technologies as well as new memory interfaces and standards.

Dave Resnick

As of the end of May ’18, am not employed. At the end was engaged at both Sandia National Laboratory and Micron Technology as a consultant for advanced memory systems and the technology that goes into them, so that memory and system performance could be improved.

Have done system engineering and system architecture work for Cray (before, during, and after it was Cray Research), Micron, Sandia, Control Data Corp, some government work, and a few others. After a BSEE degree, started work as a Customer Engineer for CDC, and actually worked for Seymore Cray for a while before he left CDC to start Cray Research.

At Micron, helped get the first generation of the Hybrid Memory Cube (HMC) going, writing a preliminary spec for the prototype parts. At Sandia looked ways that architecture and functional upgrades to high-end systems can be done to both greatly improve system performance, to do things like make memory systems more capable and intelligent, to make systems easier to use while keeping the changes and upgrades such that current codes still work, while offering upgrade paths so that the rate of acceptance of the new capabilities can be taken and used easily.

Owens Walker

Owens Walker is an Assistant Professor in the Electrical and Computer Engineering Department at the United States Naval Academy. His research interests include wireless networking, wireless security, computer security, as well as light-based communications and he leads the Naval Academy’s multi-disciplinary Computer Engineering and Cyber Security Research Team. The team is developing novel, non-invasive techniques to enhance security on storage and memory devices and their recent work has explored side-channel vulnerabilities associated with solid state drives. Owens is also a retired Naval Aviator and Navy Captain with more than 30 years of naval service spanning the North Atlantic, the Caribbean, the Indian Ocean, the Persian Gulf, and the Western Pacific.

Owens received his B.S. in Electrical Engineering from Cornell University in 1987 and both his M.S. and Ph.D. in Electrical Engineering degrees from the Naval Postgraduate School, Monterey, California in 1995 and 2009, respectively. He has been instrumental in the development of networking and cyber security course offerings at the Naval Academy. Owens is a senior member of the IEEE and a member of Eta Kappa Nu.

Ron Brightwell

Ron Brightwell leads the Scalable System Software Department at Sandia National Laboratories. After joining Sandia in 1995, he was a key contributor to the high-performance interconnect software and lightweight operating system for the world’s first terascale system, the Intel ASCI Red machine. He was also part of the team responsible for the high-performance interconnect and lightweight operating system for the Cray Red Storm machine, which was the prototype for Cray’s successful XT product line. The impact of his interconnect research is visible in technologies available today from Bull, Intel, and Mellanox. He has also contributed to the development of the MPI-2 and MPI-3 specifications. He has authored more than 115 peer-reviewed journal, conference, and workshop publications. He is an Associate Editor for the IEEE Transactions on Parallel and Distributed Systems, has served on the technical program and organizing committees for numerous high-performance and parallel computing conferences, and is a Senior Member of the IEEE and the ACM.

Michael B. Healy

Michael B. Healy is a Research Staff Member at the IBM Research T.J. Watson Research Center in Yorktown Heights, New York. His research interests cover a wide range of topics from low-level processor design to high-level system architecture. Michael's current work focuses heavily on the memory subsystem, where he contributes to the definition of the upcoming DDR5 standard. He also explores the use of 3D stacked memories such as High Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC), as well as novel 3D stacked memories with different design points for bandwidth, latency, and power tradeoffs in novel memory subsystem architectures along with emerging Non-Volatile Memories (NVM). Michael is also a core contributer to IBM's publicly available ControlleR And Memory Simulator (CramSim), which is distributed with Sandia National Laboratory's Structural Simulation Toolkit (SST) on GitHub.

Robert Ross

Robert Ross is a Senior Computer Scientist at Argonne National Laboratory and the Director of the DOE SciDAC RAPIDS Institute for Computer Science and Data. Rob’s research interests are in system software for high performance computing systems, in particular distributed storage systems and libraries for I/O and message passing. Rob received his Ph.D. in Computer Engineering from Clemson University in 2000. Rob was a recipient of the 2004 Presidential Early Career Award for Scientists and Engineers.

Ke Zhang

Ke Zhang is an Associate Professor at Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), where he received his Ph.D. in 2011. His research interests include high performance computer architecture, memory hierarchy and heterogeneous acceleration. At ICT, he leads a research and engineering team to build prototypes of new computing and storage systems for datacenter and cloud. One of their recent work is an energy-efficient and cost-effective FPGA cloud infrastructure where memory assets could be shared among different FPGA nodes. His group has been funded by the National Key Technologies Research and Development Program of China, National Natural Science Foundation of China, Strategic Priority Research Program of CAS, Xilinx and Huawei.