MEMSYS 18 Symposium Schedule

Monday, October 1st

5:00 PM - 9:00 PM - Welcome Reception

Tuesday, October 2nd

8:00 AM - Breakfast

8:50 AM - Opening Remarks

9:00 AM - Software Keynote

Brian Barrett
Principal Engineer
Amazon Web Services, Amazon

10:00 AM - Break

10:20 AM - Session 1: Datacenters and Large Memories - p.1

  • 10:20 AM - Storage-Class Memory Hierarchies for Servers - p.3
    Dmitrii Ustiugov (Ecole Polytechnique Fédérale de Lausanne), Alexandros Daglis (Ecole Polytechnique Fédérale de Lausanne), Javier Picorel (Huawei), Mark Sutherland (Ecole Polytechnique Fédérale de Lausanne), Edouard Bugnion (Ecole Polytechnique Fédérale de Lausanne), Babak Falsafi (Ecole Polytechnique Fédérale de Lausanne), Dionisios Pnevmatikatos (FORTH-ICS & ECE-TUC)
  • 10:40 AM - A Comprehensive Memory Analysis of Data Intensive Workloads on Server Class Architecture - p.19
    Hosein Mohammadi Makrani (George Mason University), Hossein Sayadi (George Mason University), Sai Manoj Pudukotai Dinakarra (George Mason University), Setareh Rafatirad (George Mason University), Houman Homayoun (George Mason University)
  • 11:00 AM - HUB: Hugepage Ballooning in Kernel-Based Virtual Machines - p.31
    Jingyuan Hu (Peking University), Xiaokuang Bai (Peking University), Sai Sha (Beijing Institute of Technology), Yingwei Luo (Peking University), Xiaolin Wang (Peking University), Zhenlin Wang (Michigan Technological University)
  • 11:20 AM - Memory Failure Prediction Using Online Learning - p.38
    Xiaoming Du (Intel), Cong Li (Intel)
  • 11:40 AM - Quantifying the Performance Overheads of PMDK - p.50
    William Wang (Arm Research), Stephan Diestelhorst (Arm Research)

12:00 PM - Conference Lunch

1:00 PM - Session 2: Memory for Parallel Systems & Architectures I - p.53

  • 1:00 PM - Improving Load Balancing for HBM Channels - p.55
    Byoungchan Oh (University of Michigan), Nam Sung Kim (University of Illinois at Urbana-Champaign), Jeongseob Ahn (Ajou University), Bingchao Li (Tianjin University), Ronald Dreslinski (University of Michigan), Trevor Mudge (University of Michigan)
  • 1:20 PM - Cooperative NV-NUMA: Prolonging Non-Volatile Memory Lifetime through Bandwidth Sharing - p.67
    Mohammad Reza Jokar (University of Chicago), Lunkai Zhang (University of Chicago), Frederic Chong (University of Chicago)
  • 1:40 PM - GraphIA: An In-situ Accelerator for Large-scale Graph Processing - p.79
    Gushu Li (University of California, Santa Barbara), Guohao Dai (Tsinghua University), Shuangchen Li (University of California, Santa Barbara), Yu Wang (Tsinghua University), Yuan Xie (University of California, Santa Barbara)
  • 2:00 PM - Dynamic Fine-Grained Sparse Memory Accesses - p.85
    Berkin Akin (Intel), Chiachen Chou (Georgia Institute of Technology), Jongsoo Park (Facebook), Chris Hughes (Intel), Rajat Agarwal (Intel)
  • 2:20 PM - Memory-Systems Challenges in Realizing Monolithic Computers - p.98
    Meenatchi Jagasivamani (University of Maryland), Candace Walden (University of Maryland), Devesh Singh (University of Maryland), Luyi Kang (University of Maryland), Shang Li (University of Maryland), Mehdi Asnaashari (Crossbar Inc.), Sylvain Dubois (Crossbar Inc.), Bruce Jacob (University of Maryland), Donald Yeung (University of Maryland)

2:40 PM - Break

3:00 PM - Session 3: DRAM Issues and Architectures - p.105

  • 3:00 PM - Accuracy of Main Memory Simulation: What are we missing? - p.107
    Rommel Sanchez Verdejo (Barcelona Supercomputing Center), Kazi Asifuzzaman (Barcelona Supercomputing Center), Radulovic Milan (Barcelona Supercomputing Center), Petar Radojkovic (Barcelona Supercomputing Center), Eduard Ayguade (Barcelona Supercomputing Center), Bruce Jacob (University of Maryland)
  • 3:20 PM - Cocoa: Synergistic Cache Compression and Error Correction in Capacity Sensitive Last Level Caches - p.117
    Chao Yan (Northwestern University), Russ Joseph (Northwestern University)
  • 3:40 PM - Opportunistic Compression for Direct-Mapped DRAM Caches - p.129
    Alaa Alameldeen (Intel), Rajat Agarwal (Intel)
  • 4:00 PM - Tackling Memory Access Latency Through DRAM Row Management - p.137
    Sriseshan Srikanth (Georgia Institute of Technology), Lavanya Subramanian (Intel), Sreenivas Subramoney (Intel), Thomas Conte (Georgia Institute of Technology), Hong Wang (Intel)
  • 4:20 PM - Efficient Coding Scheme for DDR4 Memory Subsystems - p.148
    Kira Kraft (Technische Universität Kaiserslautern), Deepak M. Mathew (Technische Universität Kaiserslautern), Chirag Sudarshan (Technische Universität Kaiserslautern), Matthias Jung (Fraunhofer), Christian Weis (Technische Universität Kaiserslautern), Norbert Wehn (Technische Universität Kaiserslautern), Florian Longnos (Huawei Technologies Co. Ltd, Data Center Technologies Lab)

4:40 PM - Break

5:00 PM - 7:00 PM - Spirited Discussion: Memory Systems Problems and Solutions

  • Keren Bergman, Columbia University
  • Phil Emma, Systems Technology & Architecture Consulting
  • Adolfy Hoisie, Brookhaven National Lab
  • Rob Ross, Argonne National Lab
  • Jeffrey Vetter, Georgia Tech & Oak Ridge National Lab
  • Ke Zhang, Institute of Computing Technology, Chinese Academy of Sciences

7:30 PM - Dinner

Regular attendees - on your own
Program Committee, Invited Speakers, Sponsors, Invited Guests - McCormick & Schmick's Harborside

Wednesday, October 3rd

8:00 AM - Breakfast

9:00 AM - Hardware Keynote

Steve Wallach
Founder of Convey, purchased by Micron, now Director of Design-Engineering

10:00 AM - Break

10:20 AM - Session 4: Memory for Parallel Systems & Architectures II - p.159

  • 10:20 AM - Trying to Link Parallel Algorithmic Thinking to Memory Systems – Extended Abstract - p.161
    James Edwards (University of Maryland), Uzi Vishkin (University of Maryland)
  • 10:40 AM - Profiled Guided Scope Based Dynamic Data Allocation Method - p.169
    Hugo Brunie (CEA), Julien Jaeger (CEA), Patrick Carribault (CEA/DAM Ile de France), Denis Barthou (Bordeaux INP)
  • 11:00 AM - High-Level Synthesis for Irregular Applications: Enabling Temporally Multithreaded Accelerators - p.183
    Stefano Devecchi (Politecnico di Milano), Nicola Saporetti (Politecnico di Milano), Marco Minutoli (Pacific Northwest National Laboratory), Vito Giovanni Castellana (Pacific Northwest National Laboratory), Marco Lattuada (Politecnico di Milano), Pietro Fezzardi (Politecnico di Milano), Fabrizio Ferrandi (Politecnico di Milano), Antonino Tumeo (Politecnico di Milano)
  • 11:20 AM - Achieving Transparency Mapping Parallel Applications: A Memory Hierarchy Affair - p.185
    Edgar A Leon (Lawrence Livermore National Laboratory), Matthieu Hautreux (French Alternative Energies and Atomic Energy Commission)
  • 11:40 AM - Hardware Transactional Persistent Memory - p.190
    Ellis Giles (Rice University), Kshitij Doshi (Intel), Peter Varman (Rice University)

12:00 PM - Conference Awards Luncheon

1:00 PM - Session 5: Modeling and Simulation - p.207

  • 1:00 PM - HMCTherm: A Cycle-accurate HMC Simulator Integrated with Detailed Power and Thermal Simulation - p.209Zhiyuan Yang (University of Maryland), Ankur Srivastava (University of Maryland)
  • 1:20 PM - Design Space Exploration of Near Memory Accelerators - p.218
    Scott Lloyd (Lawrence Livermore National Laboratory), Maya Gokhale (Lawrence Livermore National Laboratory)
  • 1:40 PM - Seeing The Data That is Not There: Estimating Data Size Through Access Sampling - p.221
    Zhizhou Zhang (University of Rochester), Chencheng Ye (Huazhong University of Science and Technology), Ning Gu (University of Rochester), Rahman Lavaee (University of Rochester), Jacob Brock (University of Rochester), Chen Ding (University of Rochester)
  • 2:00 PM - Footprint Modeling of Cache Associativity and Granularity - p.232
    Hao Luo (University of Rochester), Guoyang Chen (North Carolina State University), Fangzhou Liu (University of Rochester), Pengcheng Li (University of Rochester), Chen Ding (University of Rochester), Xipeng Shen (North Carolina State University)
  • 2:20 PM - Data-Driven Spatial Locality - p.243
    Svetozar Miucin (The University of British Columbia), Alexandra Fedorova (The University of British Columbia)

2:40 PM - Break

3:00 PM - Session 6: Exotic Technologies and Applications - p.255

  • 3:00 PM - Optically Connected and Reconfigurable GPU Architecture for Optimized Peer-to-Peer Access - p.257
    Erik Anderson (Columbia University), Jorge Gonzalez (University of Campinas), Alexander Gazman (Columbia University), Rodolfo Azevedo (University of Campinas), Keren Bergman (Columbia University)
  • 3:20 PM - Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs - p.259
    Tobias Lieske (Friedrich-Alexander-University Erlangen-Nürnberg), Mehrdad Biglari (Friedrich-Alexander University Erlangen-Nürnberg (FAU)), Dietmar Fey (University Erlangen-Nuremberg)
  • 3:40 PM - AWGR-based Optical Processor-to-Memory Communication for Low-latency, Low-energy Vault Accesses - p.269
    Sebastian Werner (University of California, Davis), Pouya Fotouhi (University of California, Davis), Roberto Proietti (University of California, Davis), S.J. Ben Yoo (University of California, Davis)
  • 4:00 PM - Leveraging MLC STT-RAM for Energy-efficient CNN Training - p.279
    Hengyu Zhao (University of California San Diego), Jishen Zhao (University of California San Diego)
  • 4:20 PM - Memory-System Requirements for Convolutional Neural Networks - p.291
  • Antara Ganguly (Indian Institute of Technology Bombay), Virendra Singh (Indian Institute of Technology Bombay), Rajeev Muralidhar (Intel)

4:40 PM - Break

5:00 PM - 7:00 PM - Spirited Discussion: New and Cool Memory Technologies

  • Shekhar Borkar, Qualcomm
  • Ron Brightwell, Sandia National Labs
  • Wendy Elsasser, Arm
  • Michael Healy, IBM
  • David Resnick, “in the process of retiring …”
  • Owens Walker, United States Naval Academy

7:30 PM - Conference Dinner & Entertainment

Bobby McKeys
(dueling piano bar)

Thursday, October 4th

8:00 AM - Breakfast

8:40 AM - Session 7: Invited Papers - p.299

  • 8:40 AM - PPT-GPU: Performance Prediction Toolkit for GPUs: Identifying the impact of caches: Extended Abstract - p.301
    Yehia Arafa (New Mexico State University), Abdel-Hameed Badawy (New Mexico State University), Gopinath Chennupati (Los Alamos National Laboratory), Nandakishore Santhi (Los Alamos National Laboratory), Stephan Eidenbenz (Los Alamos National Laboratory)
  • 9:00 AM - Open2C: Open-source Generator for Coherent Cache Memory Subsystem Exploration - p.303
    Anastasiia Butko (Lawrence Berkeley National Lab), Albert Chen (University of California, Berkeley), David Donofrio (Lawrence Berkeley National Lab), Farzad Fatollahi-Fard (Lawrence Berkeley National Lab), John Shalf (Lawrence Berkeley National Lab)
  • 9:20 AM - Demonstration of Superconducting Memory for an RQL CPU - p.313
    Randall Burnett (Northrop Grumman Corporation), Ryan Clarke (Northrop Grumman Corporation), Tim Lee (Northrop Grumman Corporation), Harold Hearne (Northrop Grumman Corporation), Jacob Vogel (Northrop Grumman Corporation), Quentin Herr (Northrop Grumman Corporation), Anna Herr (Northrop Grumman Corporation)
  • 9:40 AM - Towards Detection of Modified Firmware on Solid State Drives via Side Channel Analysis - insert
    Dane Brown (U.S. Naval Academy), Owens Walker (U.S. Naval Academy), Ryan Rakvic (U.S. Naval Academy), Robert Ives (U.S. Naval Academy), Hau Ngo (U.S. Naval Academy), James Shey (U.S. Naval Academy), Justin Blanco (U.S. Naval Academy)

10:00 AM - Break

10:20 AM - Session 8: Experiments & Optimizations - p.325

  • 10:20 AM - Architecting a Hardware-Managed Hybrid DIMM Optimized for Cost/Performance - p.327
    Fred Ware (Rambus Inc.), Javier Bueno (Metempsy), Liji Gopalakrishnan (Rambus Inc.), Brent Haukness (Rambus Inc.), Chris Haywood (Rambus Inc.), Toni Juan (Metempsy), Eric Linstadt (Rambus Inc.), Sally A McKee (Clemson University), Steven C. Woo (Rambus Inc.), Kenneth L. Wright (Rambus Inc.), Craig Hampel (Rambus Inc.), Gary Bronner (Rambus Inc.)
  • 10:40 AM - A Performance & Power Comparison of Modern High-Speed DRAM Architectures - p.341
    Shang Li (University of Maryland), Dhiraj Reddy (University of Maryland), Bruce Jacob (University of Maryland)
  • 11:00 AM - A Raspberry Pi Operating System for Exploring Advanced Memory System Concepts - p.354
    Pascal Francis-Mezger (University of Maine), Vincent Weaver (University of Maine)
  • 11:20 AM - Stake: A Coupled Simulation Environment for RISC-V Memory Experiments - p.365
    John Leidel (Tactical Computing Laboratories)
  • 11:40 AM - Driving into the Memory Wall - p.377
    Matthias Jung (Fraunhofer), Sally A. McKee (Electrical and Computer Engineering, Clemson University), Chirag Sudarshan (Technische Universität Kaiserslautern), Christoph Dropmann (Fraunhofer), Christian Weis (Technische Universität Kaiserslautern), Norbert Wehn (Technische Universität Kaiserslautern)

12:00 PM - Postamble

J. Thomas Pawlowski
Chief Technologist / Micron Fellow

Architecture Development, Micron

12:40 PM - Closing Remarks