MEMSYS 2017 Keynote Speakers

Peter M. Kogge

PETER M. KOGGE received his Ph.D. in EE from Stanford in 1973. From 1968 until 1994 he was with IBM's Federal Systems Division, and was appointed an IBM Fellow in 1993. In August, 1994 he joined the University of Notre Dame as first holder of the endowed McCourtney Chair in Computer Science and Engineering. He has served as both Department Chair and Associate Dean for Research, College of Engineering. He is an IEEE Fellow, a Distinguished Visiting Scientist at JPL, and a founder and Chief Scientist of Emu Solutions, Inc. His research interests are in massively parallel computing paradigms, processing in memory, and the relationship between massive non-numeric applications, emerging technology, and computer architectures.

He holds over 40 patents and is author of two books, including the first text on pipelining. His Ph.D. thesis led to the Kogge-Stone adder used in many microprocessors. Other projects included EXECUBE - the world's first multi-core processor and first processor on a DRAM chip, the IBM 3838 Array processor which was for a time the fastest floating point machine marketed by IBM, and the IOP - the world’s second multi-threaded parallel processor which flew on every Space Shuttle. In 2008, he led DARPA’s Exascale technology study group, which resulted in a widely referenced report on technologies and architectures for exascale computing, and has had key roles on many other HPC programs. His startup, Emu Solutions, has demonstrated the first scalable system that utilizes mobile threads to attack large-scale big data and big graph problems.

Dr. Kogge has received the Daniel Slotnick best paper award (1994), the IEEE Seymour Cray award for high performance computer engineering (2012), the IEEE Charles Babbage award for contributions to the evolution of massively parallel processing architectures (2014), the IEEE Computer Pioneer award (2015), and the Gauss best paper award for high performance computers (2015).

David Wang

David Wang is a Director of Memory Product Planning at Samsung Semiconductor Inc. Currently, David is leading Samsung's efforts in next generation memory system interconnects. David has co-authored a book on memory systems titled "Memory Systems: Cache, DRAM, Disk". Prior to joining Samsung in 2017, David was a Distinguished Engineer and Memory Systems Architect for Inphi Corporation, and before that, a lead memory systems architect for MetaRAM. David received his PhD from the University of Maryland in 2005, his PhD thesis is on the topic of a high-performance, power-constrained, DRAM-command scheduling algorithm.

Phil Emma

Dr. Philip Emma is a Fellow of the Institute of Electrical and Electronics Engineers. He recently retired as Chief Scientist from IBM TJ Watson Research Center in Yorktown Heights, NY. While his primary focus has been architecture and microarchitecture, he’s done work in many other areas throughout his career, including circuit design, packaging, memory, and transmission lines. He holds over 200 patents and has written parts of four books on these topics. He’s currently working on a book on quantum mechanics, as well as on his second novel.