MEMSYS 2017 Schedule

Mon Oct 2

Welcome Reception

5:00-9:00pm

Tues Oct 3

Breakfast

7:45am

Tue Oct 3

Opening Remarks

8:35am

Tue Oct 3

Software Keynote: Peter Kogge
Dept of Computer Science and Engineering, University of Notre Dame

8:40 am

Tue Oct 3

Break

9:40am

Tue Oct 3

Session I: Processing In and or Near Memory

Session Chair: Mike Ignatowski, AMD

 

10:00am

10:00am

AIM: Accelerating Computational Genomics through Scalable and Noninvasive Accelerator-Interposed Memory
Jason Cong (UCLA) Zhenman Fang (UCLA), Michael Gill (UCLA), Farnoosh Javadi (UCLA), Glenn Reinman (UCLA)

p. 3

10:20am

PHOENIX: Efficient Computation in Memory
Mats Rimborg (Chalmers University of Technology), Pedro Trancoso (University of Cyprus), Gunnar Carlstedt (Chalmers University of Technology)

p. 15

10:40am

Near Memory Key/Value Lookup Acceleration
Scott Lloyd (LLNL), Maya Gokhale (LLNL)

p. 26

11:00 am

The Sparse Data Reduction Engine: Chopping Sparse Data One Byte at a Time
Jonathan Beard (ARM Research)

p. 34

11:20 am

Lightweight SIMT Core Designs for Intelligent 3D Stacked DRAM
Chad Kersey (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology), Hyesoon Kim (Georgia Institute of Technology College of Computing)

p. 49

11:40 am

Identifying the Potential of Near Data Processing for Apache Spark
Ahsan Javed Awan (KTH Royal Institute of Technology), Eduard Ayguade (Technical University of Catalunya and Barcelona Super Computing Center), Kazuaki Ishizaki (IBM Research - Tokyo), Vladimir Vlassov (KTH Royal Institute of Technology), Mats Brorsson (KTH Royal Institute of Technology), Moriyoshi Ohara (IBM Research)

p. 60

Tue Oct 3

Conference Lunch

12:00 pm

Tue Oct 3

Session 2: DRAM Technolgies

Session Chair: Sally McKee, Rambus

1:00 pm

1:00 pm

A Bandwidth Accurate, Flexible and Rapid Simulating Multi-HMC Modeling Tool
Patrick Siegl (TU Braunschweig, Abteilung Technische Informatik, E.I.S.), Rainer Buchty (TU Braunschweig, Abteilung Technische Informatik, E.I.S.), Mladen Berekovic (TU Braunschweig, Abteilung Technische Informatik, E.I.S.)

p. 71

1:20pm

CramSim: Controller and Memory Simulator
Michael Healy (IBM T.J. Watson Research Center), Seokin Hong (IBM T.J. Watson Research Center)

p. 83

1:40 pm

Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact
Radhika Jagtap (ARM Ltd.), Matthias Jung (Fraunhofer IESE), Wendy Elsasser (ARM Inc.), Christian Weis (University of Kaiserslautern), Andreas Hansson (ARM Ltd.), Norbert Wehn (University of Kaiserslautern)

p. 86

2:00 pm

Odd-ECC: On-Demand DRAM Error Correcting Codes
Alirad Malek (Chalmers Univeristy), Evangelos Vasilakis (Chalmers Univeristy), Vassilis Papaefstathiou (FORTH-ICS), Pedro Trancoso (Chalmers Univeristy), Ioannis Sourdis (Chalmers University)

p. 96

2:20 pm

Evaluating Hybrid Memory Cube Infrastructure To Support High-Performance Sparse Algorithms
Kartikay Garg (Georgia Institute of Technology), Jeffrey Young (Georgia Institute of Technology)

p. 112

2:40 pm

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
Deepak M. Mathew (University of Kaiserslautern), Éder F. Zulian (University of Kaiserslautern), Matthias Jung (Fraunhofer IESE), Kira Kraft (University of Kaiserslautern), Christian Weis (University of Kaiserslautern), Bruce Jacob (University of Maryland), Norbert Wehn (University of Kaiserslautern)

p. 115

Tue Oct 3

Break

3:00 pm

Tue Oct 3

Session 3: Caches and Data Management
Session Chair: Chen Ding, University of Rochester

3:20 pm

3:20 pm

A Study of Unnecessary Write Backs
Chris Garman (Lehigh University), Xiaochen Guo (Lehigh University), Michael Spear (Lehigh University)

p. 127

3:40 pm

SprBlk Cache: Enabling Fault Resilience at Low Voltages
Nafiul Siddique (New Mexico State University), Abdel-Hameed Badawy (New Mexico State University)

p. 130

4:00 pm

Efficient STT-RAM Last-Level-Cache Architecture to Replace DRAM Cache
Fazal Hameed (Chair for Compiler Construction, Computer Science Department, TU-Dresden), Christian Menard (Chair for Compiler Construction, Computer Science Department, TU-Dresden), Jeronimo Castrillon (Chair for Compiler Construction, Computer Science Department, TU-Dresden)

p 141

4:20 pm

LMStr: Exploring Shared Hardware Controlled Scratchpad Memory for Multicores
Nafiul Siddique (New Mexico State University), Abdel-Hameed Badawy (New Mexico State University), Dave Resnick (Sandia National Laboratory), Jeanine Cook (Sandia National Laboratories)

p. 152

4:40 pm

Probabilistic Replacement Strategies for Improving the Lifetimes of NVM-Based Caches
Elizabeth Reed (University of Illinois), Alaa Alameldeen (Intel), Helia Naeimi (Intel), Patrick Stolt (Intel)

p. 166

5:00 pm

Logging in Persistent Memory: to Cache, or Not to Cache?
Mengjie Li (UC Santa Cruz), Matheus Ogleari (UC Santa Cruz), Jishen Zhao (UC Santa Cruz)

p. 177

Tue Oct 3

Break

5:20 pm

Tue Oct 3

Spirited Discussion

Memory Systems Problems and Solutions

• Chen Ding, University of Rochester
• David Donofrio, Berkeley Labs
• Scott Lloyd, LLNL
• Dave Resnick, Sandia
• Uzi Vishkin, University of Maryland

5:40 - 7:20 pm

Tue Oct 3

Dinner

Regular attendees on your own

Program Committee dinner meeting - A La Lucia, Alexandria


8:00 pm

Wed Oct 4

Breakfast

7:45 am

Wed Oct 4

Hardware Keynote: David T. Wang
Director of Memory Product Planning
Samsung

8:40 am

Wed Oct 4

Break

9:40 am

Wed Oct 4

Session 4: Next Generation Memory Technology Details
Session Chair: Robert Voigt, Northrop Grumman

10:00 am

10:00 am

Do Superconducting Processors Really Need Cryogenic Memories?
The Case for Cold DRAM
Fred Ware (Rambus), Liji Gopalakrishnan (Rambus), Eric Linstadt (Rambus), Sally A. McKee
(Rambus), Thomas Vogelsang (Rambus), Kenneth L. Wright (Rambus), Craig Hampel (Rambus), Gary
Bronner (Rambus)

p. 183

10:20 am

Cryogenic-DRAM Based Memory System for Scalable Quantum Computers: A Feasibility Study
Swamit Tannu (Georgia Institute of Technology), Douglas Carmean (Microsoft), Moinuddin Qureshi (Georgia Institute of Technology)

p. 189

10:40 am

Memory Reliability for Cells with Strong Bit-Coupling Interference
Kfir Mizrachi (Technion, Israel Institute of Technology), Ilan Bloom (Technion, Israel Institute of Technology), Yuval Cassuto (Technion, Israel Institute of Technology)

p, 196

11:00 am

Mitigating Bitline Crosstalk Noise in DRAM Memories
Seyed Mohammad Seyedzadeh (University of Pittsburgh), Donald Edward Kline Jr (University of Pittsburgh), Alex K Jones (University of Pittsburgh), Rami Melhem (University of Pittsburgh)

p. 205

11:20 am

Memristive Voltage Divider: A Bipolar ReRAM-Based Unit for Non-Volatile Flip-Flops
Mehrdad Biglari (Friedrich-Alexander University Erlangen-Nürnberg (FAU)), Dietmar Fey (Friedrich-Alexander University Erlangen-Nürnberg (FAU))

p. 217

11:40 am

Thermal-Aware, Heterogeneous Materials for Improved Energy and Reliability in 3D PCM Architectures
Heba Saadeldeen (Intel Corporation), Zhaoxia Deng (University of California, Santa Barbara), Timothy Sherwood (University of California, Santa Barbara), Fred Chong (University of Chicago)

p. 223

Wed Oct 4

Conference Lunch

12:00 pm

Wed Oct 4

Session 5: Software and Hardware Optimization Techniques
Session Chair: Scott Lloyd, LLNL

1:00 pm

1:00 pm

Memory Equalizer for Lateral Management of Heterogeneous Memory
Chen Ding (University of Rochester), Chencheng Ye (Huazhong University of Science and Technology), Hai Jin (Huazhong University of Science and Technology)

p. 239

1:20 pm

The Interaction of Last-Level-Cache Mechanisms on Modern Processors
Rakhi Hemani (IIITD), Subhasis Banerjee (IBM), Apala Guha (Indraprastha Institute of Technology)

p. 249

1:40 pm

CoMerge: Toward Efficient Data Placement in Shared Heterogeneous Memory Systems
Thaleia Dimitra Doudali (Georgia Institute of Technology), Ada Gavrilovska (Georgia Institute of Technology)

p. 251

2:00 pm

mpibind: A Memory-Centric Mapping of Hybrid Applications onto Emerging Systems
Edgar A Leon (Lawrence Livermore National Laboratory)

p. 262

2:20 pm

DRAM-Related Challenges in Task Scheduling with Timing Predictability on COTS Multi-Cores for Safety-Critical Systems
Ankit Agrawal (Technische Universität Kaiserslautern), Gerhard Fohler (Technische Universität Kaiserslautern)

p. 265

2:40 pm

BATMAN: Techniques for Maximizing System Bandwidth of Memory Systems with Stacked DRAM
Chiachen Chou (Georgia Institute of Technology), Aamer Jaleel (NVIDIA), Moinuddin Qureshi (Georgia Institute of Technology)

p. 268

Wed Oct 4

Break

3:00 pm

Wed Oct 4

Session 6: Thinking Outside the Box
Session Chair: Kenneth Wright, Rambus

3:20 pm

3:20 pm

Enabling a Reliable STT-MRAM Main Memory Simulation
Kazi Asifuzzaman (Barcelona Supercomputing Center), Rommel Sanchez Verdejo (Barcelona Supercomputing Center), Petar Radojkovic (Barcelona Supercomputing Center)

p. 283

3:40 pm

PageVault - Securing Off-Chip Memory using Page-based Authentication
Blaise Tine (Georgia Institute of Technology), Sudhakar Yalamanchili (Georgia Institute of Technology)

p. 293

4:00 pm

Long Short Term Memory Based Hardware Prefetcher
Yuan Zeng (Lehigh University), Xiaochen Guo (Lehigh University)

p. 305

4:20 pm

Task Replication and Control for Highly Parallel In-Memory Stores
Fernando Martin Del Campo (University of Toronto), Paul Chow (University of Toronto)

p. 312

4:40 pm

DyAdHyTM: A Low Overhead Dynamically Adaptive Hybrid Transactional Memory with Application to Large Graphs
Mohammad Qayum (New Mexico State University), Abdel-Hameed Badawy (New Mexico State University), Jeanine Cook (Sandia National Lab)

p. 327

5:00 pm

Rock: A Framework for Pruning the Design Space of Hybrid Main Memory Systems
Dmitry Knyaginin (Chalmers University of Technology), Per Stenstrom (Chalmers University of Technology)

p. 337

Wed Oct 4

Break

5:40 pm

Wed Oct 4

Spirited Discussion
New and Cool Memory Technologies

• Jonathan Beard, ARM
• Zeshan Chishti, Intel
• Mike Ignatowski, AMD
• Robert Voigt, Northrop Grumman
• Donald Yeung, University of Maryland

6:00 - 7:45 pm

Wed Oct 4

Conference Dinner & Awards, … and … Murder?


7:45 pm

Thu Oct 5

Breakfast

7:15 am

Thu Oct 5

Systems Keynote: Phil Emma, Chief Scientist (recently retired)
IBM

8:40 am

Thu Oct 5

Break

9:40 am

Thu Oct 5

Session 7: Management of Non-Volatile Memories
Session Chair: David Donofrio, Berkeley Labs

10:00 am

10:00 am

NEMO: An Energy-Efficient Hybrid Main Memory System for Mobile Devices
Bahareh Pourshirazi (University of Illinois at Chicago), Zhichun Zhu (University of Illinois at Chicago)

p. 351

10:20 am

Composing Lifetime Enhancing Techniques for Non-Volatile Main Memories
Andres Amaya Garcia (ARM Ltd.), William Wang (ARM Ltd.), Rene de Jong (ARM Ltd.), Stephan Diestelhorst (ARM Ltd.)

p. 363

10:40 am

Improving SSD Lifetime with Byte-Addressable Metadata
Yanqin Jin (University of California, San Diego), Hung-Wei Tseng (North Carolina State University), Yannis Papakonstantinou (University of California, San Diego), Steven Swanson (University of California, San Diego)

p. 374

11:00 am

REMAP: A Reliability/Endurance Mechanism for Advancing PCM
Mohammad Khavari Tavana (Northeastern University), Amir Kavyan Ziabari (Northeastern University), Mohammad Arjomand (Pennsylvania State University), Mahmut Kandemir (Pennsylvania State University), Chita Das (Pennsylvania State University), David Kaeli (Northeastern University)

p. 385

11:20 am

Speculative Paging for Future NVM and SSD
Viacheslav Fedorov (Texas A&M University), Jinchun Kim (Texas A&M University), Mian Qin (Texas A&M University), A. L. Narasimha Reddy (Texas A&M University), Paul Gratz (Texas A&M University)

p. 399

11:40 am

Performance Analysis for Using Non-Volatile Memory DIMMs: Opportunities and Challenges
Amro Awad (Sandia National Laboratories), Simon Hammond (Sandia National Laboratories), Clay Hughes (Sandia National Laboratories), Arun Rodrigues (Sandia National Laboratories), Scott Hemmert (Sandia National Laboratories), Robert Hoekstra (Sandia National Laboratories)

p. 411

Thu Oct 5

Closing Remarks

12:00 pm