Sept. 28 – Oct 2, Washington DC

Join us for our

Welcome Reception & Poster Competition

Monday Evening • Sept. 30th • 5 to 9 pm at the Arlington Westin

Tuesday, October 1st

10:00 AM – Session 1:

In-Memory Mechanisms – p.1


  • 10:00 AM – NEMESYS: Near-Memory Graph Copy Enhanced System-Software – p.3, Sven Rheindt (Technical University of Munich), Andreas Fried, (Karlsruhe Institute of Technology), Oliver Lenke (Technical University of Munich), Lars Nolte (Technical University of Munich), Thomas Wild (Technical University of Munich), Andreas Herkersdorf (Technical University of Munich)
  • 10:20 AM – A Computation-In-Memory ccelerator Based on Resistive Devices – p.19, Hoang Anh Du Nguyen (Delft University of Technology), Jintao Yu (Delft University of Technology), Muath Abu Lebdeh (Delft University of Technology), Mottaqiallah Taouil (Delft University of Technology), Said Hamdioui (Delft University of Technology)
  • 10:40 AM – Attacking Memory-Hard scrypt with Near-Data-Processing – p.33, Jiwon Choe (Brown University), Tali Moreshet (Boston University), R. Iris Bahar (Brown University), Maurice Herlihy (Brown University)
  • 11:00 AM – Digital-based Processing In-Memory: A Highly-Parallel Accelerator for Data Intensive Applications – p.38, Mohsen Imani (University of California San Diego), Saransh Gupta (University of California San Diego), Tajana Rosing (University of California San Diego)
  • 11:20 AM – PIMS: A Lightweight Processing-in-Memory Accelerator for Stencil Computations – p.41, Jie Li (Texas Tech University), Xi Wang (Texas Tech University), Antonino Tumeo (Pacific Northwest National Laboratory), Brody Williams (Texas Tech University), John D. Leidel (Tactical Computing Labs), Yong Chen (Texas Tech University)
  • 11:40 AM – Fast In-Memory CRIU for Docker Containers – p.53, Ranjan Sarpangala Venkatesh (Georgia Institute of Technology), Till Smejkal (TU Dresden), Dejan S. Milojicic (Hewlett Packard Enterprise), Ada Gavrilovska (Georgia Institute of Technology)

1:00 PM – Session 2:

Errors, Endurance, Validation, Resilience – p.67


  • 1:00 PM – DRAM Errors in the Field: A Statistical Approach – p.69, Darko Zivanovic (Barcelona Supercomputing Center), Pouya Esmaili-Dokht (Barcelona Supercomputing Center), Sergi More (Barcelona Supercomputing Center), Javier Bartolome (Barcelona Supercomputing Center), Paul Carpenter (Barcelona Supercomputing Center), Petar Radojkovic (Barcelona Supercomputing Center), Eduard Ayguade (Barcelona Supercomputing Center & Universitat Politecnica de Catalunya)
  • 1:20 PM – Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories – p.85, Irina Alam (University of California, Los Angeles), Saptadeep Pal (University of California, Los Angeles), Puneet Gupta (University of California, Los Angeles)
  • 1:40 PM – Endurance Enhancement of Write-Optimized STT-RAM Caches – p.101, Puneet Saraf (Indian Institute of Technology Madras, Chennai), Madhu Mutyam (Indian Institute of Technology, Madras. Chennai)
  • 2:00 PM – Transitioning Scientific Applications to using Non-Volatile Memory for Resilience – p.114, Brandon Nesterenko (University of Colorado Colorado Springs), Xiao Liu (University of California San Diego), Qing Yi (University of Colorado Colorado Springs), Jishen Zhao (University of California San Diego), Jiange Zhang (University of Colorado Colorado Springs)
  • 2:20 PM – Combining Error Statistics with Failure Prediction in Memory Page Offlining – p.127, Xiaoming Du (Intel), Cong Li (Intel)
  • 2:40 PM – Fast Validation of DRAM Protocols with Timed Petri Nets – p.133, Matthias Jung (Fraunhofer), Kira Kraft (Technische Universität Kaiserslautern), Taha Soliman (Technische Universität Kaiserslautern), Chirag Sudarshan (Technische Universität Kaiserslautern), Christian Weis (Technische Universität Kaiserslautern), Norbert Wehn (Technische Universität Kaiserslautern)

3:20 PM – Session 3:

Modeling & Optimization – p.147


  • 3:20 PM – M&MMs: Navigating Complex Memory Spaces with hwloc – p.149, Edgar A. Leon (Lawrence Livermore National Laboratory), Brice Goglin (Inria, LaBRI, Univ. Bordeaux), Andres Rubio Proaño (Inria, LaBRI, Univ. Bordeaux)
  • 3:40 PM – Portable Application Guidance for Complex Memory Systems – p.156, M. Ben Olson (University of Tennessee), Brandon Kammerdiener (University of Tennessee), Michael R. Jantz (University of Tennessee), Kshitij A. Doshi (Intel), Terry Jones (Oak Ridge National Laboratory)
  • 4:00 PM – Hopscotch: A Micro-benchmark Suite for Memory Performance Evaluation – p.167, Alif Ahmed (University of Virginia), Kevin Skadron (University of Virginia)
  • 4:20 PM – A Unifying Abstraction for Data Structure Splicing – p.173, Louis Ye (The University of British Columbia), Mieszko Lis (The University of British Columbia), Alexandra Fedorova (The University of
  • British Columbia)
  • 4:40 PM – Rethinking Cycle-accurate DRAM Simulation – p.184, Shang Li (University of Maryland), Rommel Verdejo (Universitat Politècnica de Catalunya), Petar adojković (Universitat Politècnica de Catalunya), Bruce Jacob (University of Maryland)

Wednesday, October 2nd

10:00 AM – Session 4:

Redesigning & Rethinking – p.193


  • 10:00 AM – STT-MRAM for Real-Time Embedded Systems: Performance and WCET Implications – p.195, Kazi Asifuzzaman (Barcelona Supercomputing Center), Mikel Fernandez (Barcelona Supercomputing Center), Petar Radojkovic (Barcelona Supercomputing Center), Jaume Abella (Barcelona Supercomputing Center), Francisco J. Cazorla (Barcelona Supercomputing Center)
  • 10:20 AM – 3D Photonics as Enabling Technology for Deep 3D DRAM Stacking – p.206, Sebastian Werner (University of California, Davis), Pouya Fotouhi (University of California, Davis), George Michelogiannakis (Lawrence Berkeley National Laboratory), Dilip Vasudevan (Lawrence Berkeley National Laboratory), S.J. Ben Yoo (University of California, Davis)
  • 10:40 AM – Enabling Scalable Chiplet-based Uniform Memory Architectures with Silicon Photonics – p.222, Pouya Fotouhi (University of California, Davis), Sebastian Werner (University of California, Davis), Jason Lowe-Power (University of California, Davis), S. J. Ben Yoo (University of California, Davis)
  • 11:00 AM – Scaling The Capacity of Memory Systems;Evolution and Key Approaches – p.235, Kyriakos Paraskevas (The University of Manchester), Andrew Attwood (The University of Manchester), Mikel Lujan (The University of Manchester), John Goodacre (The University of Manchester)
  • 11:20 AM – Data Broker: a Case for Workflow Enablement Using a Key/Value Approach – p.250, Lars Schneidenbach (IBM), Bruce D’Amora (IBM), Claudia Misale (IBM), Carlos H.A. Costa (IBM), Sara Kokkila Schumacher (IBM), Thomas Ward (IBM Hursley)
  • 11:40 AM – Towards a Scatter-Gather Architecture – p.261, Arun Rodrigues (Sandia National Labs), Maya Gokhale (Lawrence Livermore National Laboratory), Gwendolyn Voskuilen (Sandia National Labs)

1:00 PM – Session 5:

Non-Volatile Main Memories – p.275


  • 1:00 PM – Evaluation of Intel 3D-Xpoint NVDIMM Technology for Memory-Intensive Genomic Workloads – p.277, Daniel Waddington (IBM), Mark Kunitomi (IBM), Clem Dickey (IBM), Samyukta Rao (IBM), Amir Abboud (IBM), Jantz Tran (Intel Corporation)
  • 1:20 PM – Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using Intel Optane DC Persistent Memory Modules – p.288, Onkar Patil (North Carolina State University), Latchesar Ionkov (Los Alamos National Laboratory), Jason Lee (Los Alamos National Laboratory), Frank Mueller (North Carolina State University), Michael Lang (Los Alamos National Laboratory)
  • 1:40 PM – System Evaluation of the Intel Optane Byte-addressable NVM – p.304, Ivy B. Peng (Lawrence Livermore National Laboratory), Maya B. Gokhale, (Lawrence Livermore National Laboratory), Eric W. Green (Lawrence Livermore National Laboratory)
  • 2:00 PM – SMART: STT-MRAM Architecture for Smart Activation and Sensing – p.316,
  • Byoungchan Oh (University of Michigan), Nam Sung Kim (University of Illinois at Urbana-Champaign), Nilmini Abeyratne (University of Michigan), Ronald Dreslinski (University of Michigan), Trevor Mudge (University of Michigan)
  • 2:20 PM – Simultaneously Reducing Cost and Improving Performance of NVM-based Block Devices via Transparent Data Compression – p.331, Xubin Chen (Rensselaer Polytechnic Institute), Yin Li (Rensselaer Polytechnic Institute), Jingpeng Hao (Rensselaer Polytechnic Institute), Hyunsuk Shin (Qualcomm), Michael Suh (Qualcomm), Tong Zhang (Rensselaer Polytechnic Institute)
  • 2:40 PM – Design for ReRAM-based Main-Memory Architectures – p.342, Meenatchi Jagasivamani (University of Maryland), Candace Walden, (University of Maryland), Devesh Singh (University of Maryland), Luyi Kang (University of Maryland), Shang Li (University of Maryland), Mehdi Asnaashari (Crossbar, Inc.), Sylvain Dubois (Crossbar, Inc.), Donald Yeung (University of Maryland), Bruce Jacob (University of Maryland)

3:20 PM – Session 6:

Memory-Targeted Compiler Optimizations – p.351


  • 3:20 PM – Faster Slab Reassignment in Memcached – p.353, Daniel Byrne (Michigan Technological University), Nilufer Onder (Michigan Technological University), Zhenlin Wang (Michigan Technological University)
  • 3:40 PM – LLAMA — Automatic Memory Allocations – p.363, Derrick Greenspan (University of Central Florida)4:00 PM – FAPS-3D: Feedback-directed Adaptive Page Management Scheme for 3D-Stacked DRAM – p.373, Muhammad Rafique (University of Illinois at Chicago, Chicago, IL. USA.), Zhichun Zhu (University of Illinois at Chicago, Chicago, IL. USA.)
  • 4:20 PM – Evaluating the Effectiveness of Program Data Features for Guiding Memory Management – p.383, T. Chad Effler (University of Tennessee), Brandon Kammerdiener (University of Tennessee), Michael R. Jantz (University of Tennessee), Saikat Sengupta (University of Kansas), Prasad A. Kulkarni (University of Kansas), Kshitij A. Doshi (Intel), Terry Jones (Oak Ridge National Laboratory)
  • 4:40 PM – CASH: Compiler Assisted Hardware Design for Improving DRAM Energy Efficiency in CNN Inference – p.396, Anup Sarma (The Pennsylvania State University), Huaipan Jiang (The Pennsylvania State University), Ashutosh Pattnaik (The Pennsylvania State University), Jagadish Kotra (The Pennsylvania State University), Mahmut Taylan Kandemir (The Pennsylvania State University), Chita R. Das (The Pennsylvania State University)

Thursday, October 3rd

8:40 AM – Session 7:

Caching & Cache Techniques – p.409


  • 8:40 AM – Statistical Caching for Near Memory Management – p.411, Dong Chen (National University of Defense Technology), Fangzhou Liu (University of Rochester), Mingyang Jiao (University of Rochester), Chen Ding (University of Rochester), Sreepathi Pai (University of Rochester)
  • 9:00 AM – Page Migration Support for Disaggregated Non-Volatile Memories – p.417, Vamsee Reddy Kommareddy (University of Central Florida), Clayton Hughes (Sandia National Laboratories), Simon David Hammond (Sandia National Laboratories), Ahmad Samih (Intel), Amro Awad (University of Central Florida)
  • 9:20 AM – The Impact of Cache Inclusion Policies on Cache Management Techniques – p.428, Luna Backes (Texas A&M University), Daniel A. Jiménez (Texas A&M University and Barcelona Supercomputing Center)
  • 9:40 AM – ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors – p.439, Dhruv Gajaria (University of Arizona), Tosiron Adegbija (University of Arizona)
  • 10:00 AM – RRS Cache: A Low Voltage Cache based on Timing Speculation SRAM with a Reuse-aware Cacheline Remapping Mechanism – p.451, Xiaojing Shang (National ASIC Research Center), Ming Ling (National ASIC Research Center), Shan Shen (National ASIC Research Center), Tianxiang Shao (National ASIC Research Center), Jun Yang (National ASIC Research Center)

10:40 AM – Session 8:

Machine Learning – p.459


  • 10:40 AM – Predicting Memory Accesses: The Road to Compact ML-driven Prefetcher – p.461, Ajitesh Srivastava (University of Southern California), Angelos Lazaris (University of Southern California), Benjamin Brooks (University of Southern California), Rajgopal Kannan (Army Research Lab – West), Viktor Prasanna (University of Southern California)
  • 11:00 AM – Inference Engine Benchmarking Across Technological Platforms from CMOS to RRAM – p.471, Xiaochen Peng (Georgia Institute of Technology), Minkyu Kim (Arizona State University), Xiaoyu Sun (Georgia Institute of Technology), Shihui Yin (Arizona State University), Titash Rakshit (Samsung Semiconductor Inc.), Ryan M. Hatcher (Samsung Semiconductor Inc.), Jorge A. Kittl (Samsung Semiconductor Inc.), Jae-Sun Seo (Arizona State University), Shimeng Yu (Georgia Institute of Technology)
  • 11:20 AM – Machine Learning Based Design Space Exploration for Hybrid Main-Memory Design – p.480, Satyabrata Sen (Oak Ridge National Laboratory), Neena Imam (Oak Ridge National Lab)
  • 11:40 AM – CIMAT: A Transpose SRAM-based Compute-In-Memory Architecture for Deep Neural Network On-Chip Training – p.490, Hongwu Jiang (Georgia Institute of Technology), Xiaochen Peng (Georgia Institute of Technology), Shanshi Huang (Georgia Institute of Technology), Shimeng Yu (Georgia Institute of Technology)
  • 12:00 PM – Memory System Characterization of Deep Learning Workloads – p.497, Zeshan Chishti (Intel), Berkin Akin (Google)
  • 12:20 PM – Co-ML: A Case for Collaborative ML Acceleration using Near-data Processing – p.506, Shaizeen Aga (AMD Research), Nuwan Jayasena (AMD Research), Mike Ignatowski (AMD Research)

Invited Papers:

from New and Cool Tech panel


  • Statistical DRAM Modeling – p.521, Shang Li (University of Maryland), Bruce Jacob (University of Maryland)
  • Demonstration of Superconducting Memory with Passive Transmission Line-Based Reads – p.531, Randal Posey (Northrop Grumman), Randall Burnett (Northrop Grumman), Quentin Herr (Northrop Grumman), Don Miller (Northrop Grumman)